12 de marzo de 2005


Es curioso, el otro día me encontré un libro que se titulaba "the alpha reference manual" o algo así y lo cogí (no deberían dejar esos libros a la vista entre la bibliografía de las asignaturas...), y venía un párrafo de los diseñadores del procesador. Es uno de esos párrafos que lo lees y dices "wow". Un testimonio de lo que era Digital. Su objetivo era crear un procesador que sirviera de plataforma durante 15-25 años, como lo había sido el VAX. Tambien eran conscientes de que la velocidad de los procesadores había aumentado mil veces en los últimos 25 años, y Alpha fue diseñado para poder lograr tambien ese aumento a lo largo de su vida, siendo conscientes de que iban a necesitar smp/cores en el futuro para continuar con ese aumento, etc. En otras palabras: una arquitectura aun joven que si alguien se hubiera molestado en continuar fabricando, podria patear a muchos.

En fin. Como curiosidad, he encontrado el dichoso párrafo por internet

4 Architectural Goals

When we started the detailed design of the Alpha AXP architecture, we had a short list of goals:

1. High performance
2. Longevity
3. Capability to run both VMS and UNIX operating systems
4. Easy migration from VAX and MIPS architectures

These goals directly influenced our key decisions in designing the architecture.
In considering performance and longevity, we set a 15- to 25-year design horizon and tried to avoid any design elements that we thought could become limitations during this time. In current architectures, a primary limitation is the 32-bit memory address. Thus we adopted a full 64-bit architecture, with a minimal number of 32-bit operations for backward compatibility.

We also considered how implementation performance should scale over 25 years. During the past 25 years, computers have become about 1,000 times faster. Therefore we focused our design decisions on allowing Alpha AXP system implementations to become 1,000 times faster over the coming 25 years. In our projections of future performance, we reasoned that raw clock rates would improve by a factor of 10 over that time, and that other design dimensions would have to provide two more factors of 10.

If the clock cannot be made faster, then more work must be done per clock tick. We therefore designed the Alpha AXP architecture to encourage multiple instruction issue* implementations that will eventually sustain about ten new instructions starting every clock cycle. This aggressive technique of starting multiple instructions distinguishes the Alpha AXP architecture from many other RISC architectures.

The remaining factor of 10 will come from multiple processors. A single system will contain perhaps ten processors and share memory. We therefore designed a multiprocessor memory model and matching instructions from the beginning. This early accommodation for multiple processors also distinguishes the Alpha AXP architecture from many other RISC architectures, which try to add the proper primitives later.

To run the OpenVMS AXP and the DEC OSF/1 AXP-and now the Microsoft Windows NT-operating systems, we adopted an idea from a previous Digital RISC design called PRISM.[3] We placed the nderpinnings for interrupt delivery and return, exceptions, context switching, memory management, and error handling in a set of privileged software subroutines called PALcode. These subroutines have controlled entry points, run with interrupts turned off, and have access to real hardware (implementation) registers. By including different sets of PALcode for different operating systems, neither the hardware nor the operating system is burdened with a bad interface match, and the architecture itself is not biased toward a particular computing style.

El resto, aquí

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